Understanding the hardware is crucial for efficient testing. The V93000 is highly configurable, with different classes determined by the tester size (e.g., Pin Scale 1600, Pin Scale 9G).
An automated software utility that aligns signal arrival times across all pins. It compensates for internal board trace propagation delays, cable variances, and temperature drifts.
Allows independent digital patterns to execute asynchronously or synchronously across different ports, slashing overall Test Time ( Ttestcap T sub t e s t end-sub 3. Developing Digital Patterns and Vector Compilation
This phenomenon suggests that the official manual, while accurate, lacks context. It describes the "AV8" pin card’s drive bandwidth in meticulous detail, but it may not sufficiently explain how to compensate for signal integrity loss at the load board interface. The gap between the manual's theoretical capabilities and the practical reality of a test cell is often bridged by experienced peers rather than the official text.
Test methods are executable software blocks written in C++ (SmarTest 7/8) or Java (SmarTest 8) that control the tester hardware. They extract data from the hardware registers, calculate parameters, and flag pass/fail criteria. Standard pre-coded test methods are provided by Advantest for typical tests, including: Continuity/Diode tests Leakage tests ( IILcap I sub cap I cap L end-sub IIHcap I sub cap I cap H end-sub IDD Gross/Static current consumption Functional vector execution Writing a Custom Functional Test Suite verigy 93k tester manual
Documentation on developing C++ test programs using Universal Test Method (UTM) libraries (e.g., dc_tml , ac_tml , scan_tml ). 3. Key Technical Concepts in Documentation
The Verigy 93K is a high-performance automated test equipment (ATE) platform used for digital, mixed-signal, and RF semiconductor testing. A tester manual for the 93K typically covers hardware architecture, software interface (including test program development and execution), maintenance procedures, safety guidelines, and troubleshooting. This report summarizes typical manual contents, key sections to look for, common procedures, and recommendations for obtaining and using the official manual.
The tester is a highly scalable Automated Test Equipment (ATE) platform used for semiconductor testing, covering everything from simple microcontrollers to complex SoCs, RF, and High-Speed I/O devices.
To run a functional pattern and check for pass or fail conditions, you use the functional burst API tools: Understanding the hardware is crucial for efficient testing
Specifications for designing the interface between the tester and the Device Under Test (DUT). 2.3 SmarTest Software Development Guide
) through the PPMU to bias protection diodes. It measures the resulting voltage drop to confirm a solid electrical connection. Gross Leakage ( IIHcap I sub cap I cap H end-sub IILcap I sub cap I cap L end-sub
Checks the physical connection between the tester probe/socket and the chip. It utilizes the protection diodes present on CMOS I/O pins by forcing a small current (e.g., ) and measuring the forward voltage drop. Gross Leakage (
Tester Channel=Slot Number+Card Channel NumberTester Channel equals Slot Number plus Card Channel Number It compensates for internal board trace propagation delays,
Program the precise DC voltages and timing cycles required by your device specification sheet.
I can provide step-by-step code examples or hardware pinouts based on your needs. Share public link
Detailed info on pin scale cards (e.g., PS1600 , PS9G ) and DC scale instruments like DPS128 or UHC4 .
Do not exceed maximum potential ratings on any terminal.