2021 [verified] | Synopsys Design Compiler Tutorial
: The command-line interface, ideal for professional automation and scripting using Tcl. Design Vision
Or run in batch mode from the Linux shell:
# Define the primary clock (Period in nanoseconds) create_clock -name sys_clk -period 2.0 [get_ports clk] # Model clock uncertainty (Jitter and Skew) set_clock_uncertainty 0.15 [get_clocks sys_clk] # Define Input and Output delays relative to the clock edge set_input_delay 0.4 -clock sys_clk [remove_from_collection [all_inputs] [get_ports clk]] set_output_delay 0.4 -clock sys_clk [all_outputs] # Model electrical environment attributes set_driving_cell -lib_cell BUFX2 [remove_from_collection [all_inputs] [get_ports clk]] set_load [load_of typical/BUFX4/A] [all_outputs] # Set operating conditions set_operating_conditions -max "typical" Use code with caution. Step 3: Compiling and Optimizing the Design
write -format ddc -hierarchy -output ./results/top_synth.ddc synopsys design compiler tutorial 2021
# Create a directory to store structural reports file mkdir reports # Generate timing, area, power, and constraint reports report_design > reports/design.rpt report_area -hierarchy > reports/area.rpt report_power -hierarchy > reports/power.rpt report_constraint -all_violators > reports/violators.rpt report_timing -delay max -max_paths 10 > reports/timing_setup.rpt report_timing -delay min -max_paths 10 > reports/timing_hold.rpt Use code with caution. 7. Exporting the Gate-Level Netlist
With the design loaded and constraints applied, you can compile the logic. Standard synthesis uses wireload models, while Topographical Mode uses physical data from a floorplan to calculate accurate interconnect delays. Running Basic Compile
############################################################################### # Synopsys Design Compiler Synthesis Automation Script ############################################################################### # 1. Define Design and File Variables set DESIGN_NAME "my_design" set RTL_FILES [list my_design.sv controller.sv datapath.sv] set REPORT_DIR "../output/reports" set NETLIST_DIR "../output/netlist" # 2. Analyze and Elaborate RTL analyze -format sverilog $RTL_FILES elaborate $DESIGN_NAME current_design $DESIGN_NAME # 3. Link and Verify Structure link check_design > "$REPORT_DIR/check_design_init.rpt" # 4. Apply Synthesis Constraints create_clock -name sys_clk -period 2.0 [get_ports clk] set_clock_uncertainty 0.15 [get_clocks sys_clk] set_input_delay 0.4 -clock sys_clk [remove_from_collection [all_inputs] [get_ports clk]] set_output_delay 0.4 -clock sys_clk [all_outputs] set_driving_cell -lib_cell BUFX2 [remove_from_collection [all_inputs] [get_ports clk]] set_load [load_of typical/BUFX4/A] [all_outputs] # 5. Execute Compile Engine compile_ultra # 6. Generate Performance Reports report_area -hierarchy > "$REPORT_DIR/area.rpt" report_timing -delay max -path full > "$REPORT_DIR/timing.rpt" report_power -hierarchy > "$REPORT_DIR/power.rpt" report_constraint -all_violators > "$REPORT_DIR/violators.rpt" # 7. Export Physical Design Deliverables change_names -rules verilog -hierarchy write -format verilog -hierarchy -output "$NETLIST_DIR/$DESIGN_NAME.v" write_sdc "$NETLIST_DIR/$DESIGN_NAME.sdc" write -format ddc -hierarchy -output "$NETLIST_DIR/$DESIGN_NAME.ddc" echo "Synthesis script completed successfully." exit Use code with caution. 6. Interpreting Timing Reports : The command-line interface
# Create a primary clock named 'sys_clk' with a 10ns period on port 'clk' create_clock -name sys_clk -period 10.0 [get_ports clk] # Model clock jitter and routing delay (skew) using uncertainty set_clock_uncertainty 0.25 [get_clocks sys_clk] # Define clock transition times (slew rate) set_clock_transition 0.15 [get_clocks sys_clk] Use code with caution. Input and Output Delays
Master the Flow: A 2021 Guide to Synopsys Design Compiler Synopsys Design Compiler (DC) remains the industry-standard engine for transforming Register Transfer Level (RTL) descriptions into gate-level netlists. In 2021, the landscape evolved with the introduction of Design Compiler NXT , bringing advanced capabilities for 5nm nodes and beyond.
dc.read_verilog(['rv32i_core.v', 'alu.v']) dc.current_design('rv32i_core') dc.create_clock('clk', period=1.0) dc.compile_ultra(timing_high_effort=True) dc.write_verilog('outputs/rv32i_core.v') synopsys design compiler tutorial 2021
# Define Clock create_clock -name CLK -period 1.0 [get_ports clk] set_clock_uncertainty 0.1 [get_clocks CLK] # Define Input/Output Delays set_input_delay -max 0.5 -clock CLK [all_inputs] set_output_delay -max 0.5 -clock CLK [all_outputs] # Set Area Constraint set_max_area 0 Use code with caution. Phase 3: Synthesis and Optimization
These commands define the target operating frequency and account for real-world variations in the clock network.